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1/11 august 2001 n high speed: f max = 90mhz (typ.) at v cc = 6v n low power dissipation: i cc = 4 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n symmetrical output impedance: |i oh | = i ol = 6ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 564 description the m74hc564 is an high speed cmos octal d-type flip flop with 3-state outputs inverting fabricated with silicon gate c 2 mos technology. this 8 bit d-type flip flop is controlled by a clock input (ck) and an output enable input (oe ). on the positive transition of the clock, the q outputs will be set to the logic state that were setup at the d inputs. while the oe input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. the output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc564 octal d-type flip flop with 3 state output inverting pin connection and iec logic symbols order codes package tube t & r dip m74hc564b1r sop M74HC564M1R m74hc564rm13tr tssop m74hc564ttr tssop dip sop
m74hc564 2/11 input and output equivalent circuit pin description truth table x: dont care z: high impedance logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1oe 3 state output enable input (active low) 2, 3, 4, 5, 6, 7, 8, 9, 10 d0 to d7 data inputs 12, 13, 14, 15, 16, 17, 18, 19 q0 to q7 3 state outputs 11 clock clock input (low to high, edge triggered) 10 gnd ground (0v) 20 v cc positive supply voltage inputs output oe ck d q hxxz l x no change llh lhl
m74hc564 3/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc564 4/11 dc specification symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.60 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.33 0.40 6.0 i o =7.8 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i = v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i = v ih or v il v o = v cc or gnd 0.5 5 10 m a i cc quiescent supply current 6.0 v i = v cc or gnd 44080 m a
m74hc564 5/11 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8(per flip-fllop) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 50 25 60 75 90 ns 4.5 7121518 6.0 6101315 t plh t phl propagation delay time (ck - q ) 2.0 50 70 150 190 225 ns 4.5 20 30 38 45 6.0 15 26 32 38 2.0 150 88 190 240 285 ns 4.5 25 38 48 57 6.0 19 32 41 48 t pzl t pzh high impedance output enable time 2.0 50 r l = 1 k w 48 125 155 190 ns 4.5 15 25 31 38 6.0 12 21 26 32 2.0 150 r l = 1 k w 60 165 205 250 ns 4.5 20 33 41 50 6.0 16 28 35 43 t plz t phz high impedance output disable time 2.0 50 r l = 1 k w 34 125 155 190 ns 4.5 17 25 31 38 6.0 15 21 26 32 f max maximum clock frequency 2.0 50 6.2 18 5 4.2 mhz 4.5 31 75 25 21 6.0 37 90 30 25 t w(l) t w(h) minimum pulse width (ck) 2.0 50 15 75 95 110 ns 4.5 6151922 6.0 6131619 t s minimum set-up time 2.0 50 25 75 95 110 ns 4.5 6151922 6.0 4131619 t h minimum hold time 2.0 50 000 ns 4.5 0 0 0 6.0 0 0 0 symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c out output capacitance 10 pf c pd power dissipation capacitance (note 1) 54 pf
m74hc564 6/11 test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) waveform 1: ck to qn propagation delays, dn to ck setup and hold times, ck maximum frequency (f=1mhz; 50% duty cycle) test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd
m74hc564 7/11 waveform 2: output enable and disable times (f=1mhz; 50% duty cycle) waveform 3: ck minimum pulse width (f=1mhz; 50% duty cycle)
m74hc564 8/11 dim. mm. inch min. typ max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 plastic dip-20 (0.25) mechanical data p001j
m74hc564 9/11 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
m74hc564 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
m74hc564 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 11/11

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